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DATA SHEET
MOS INTEGRATED CIRCUIT
PD44323362
32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The PD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The PD44323362 is suitable for applications which require high-speed, low voltage, high-density memory and wide bit configuration, such as cache and buffer memory. The PD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
* Fully synchronous operation * HSTL Input / Output levels * Fast clock access time: 2.0 ns / 250 MHz * Asynchronous output enable control: /G * Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9) * Common I/O using three-state outputs * Internally self-timed write cycle * Late write with 1 dead cycle between Read-Write * User-configurable outputs: Controlled impedance outputs or push-pull outputs * Boundary scan (JTAG) IEEE 1149.1 compatible * 2.5 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply * 119 bump BGA package, 1.27 mm pitch, 14 mm x 22 mm * Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number Access time 2.0 ns Clock frequency 250 MHz Package 119-pin PLASTIC BGA
PD44323362F1-C40-FJ1
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
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Document No. M16379EJ4V0DS00 (4th edition) Date Published May 2004 NS CP(K) Printed in Japan
The mark
shows major revised points.
2002
PD44323362
Pin Configuration
/xxx indicates active low signal. 119-pin plastic BGA
Top View A B C D E F G H J K L M N P R T U 1234567
1 VDDQ NC NC DQc8 DQc6 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ DQd6 DQd8 NC NC VDDQ 2 SA12 SA18 SA13 DQc9 DQc7 DQc5 DQc4 DQc2 VDD DQd2 DQd4 DQd5 DQd7 DQd9 SA14 NC TMS 3 SA9 SA16 SA10 VSS VSS VSS /SBc VSS VREF VSS /SBd VSS VSS VSS M1 SA11 TDI 4 NC SA19 VDD ZQ /SS /G NC NC VDD K /K /SW SA0 SA1 VDD SA8 TCK 5 SA5 SA15 SA6 VSS VSS VSS /SBb VSS VREF VSS /SBa VSS VSS VSS M2 SA7 TDO 6 SA2 SA17 SA3 DQb9 DQb7 DQb5 DQb4 DQb2 VDD DQa2 DQa4 DQa5 DQa7 DQa9 SA4 NC NC 7 VDDQ NC NC DQb8 DQb6 VDDQ DQb3 DQb1 VDDQ DQa1 DQa3 VDDQ DQa6 DQa8 NC ZZ VDDQ A B C D E F G H J K L M N P R T U 7 VDDQ NC NC DQb8 DQb6 VDDQ DQb3 DQb1 VDDQ DQa1 DQa3 VDDQ DQa6 DQa8 NC ZZ VDDQ
Bottom View
7654321
6 SA2 SA17 SA3 DQb9 DQb7 DQb5 DQb4 DQb2 VDD DQa2 DQa4 DQa5 DQa7 DQa9 SA4 NC NC 5 SA5 SA15 SA6 VSS VSS VSS /SBb VSS VREF VSS /SBa VSS VSS VSS M2 SA7 TDO 4 NC SA19 VDD ZQ /SS /G NC NC VDD K /K /SW SA0 SA1 VDD SA8 TCK 3 SA9 SA16 SA10 VSS VSS VSS /SBc VSS VREF VSS /SBd VSS VSS VSS M1 SA11 TDI 2 SA12 SA18 SA13 DQc9 DQc7 DQc5 DQc4 DQc2 VDD DQd2 DQd4 DQd5 DQd7 DQd9 SA14 NC TMS 1 VDDQ NC NC DQc8 DQc6 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ DQd6 DQd8 NC NC VDDQ
2
Data Sheet M16379EJ4V0DS
PD44323362
Pin Name and Functions
Pin name VDD VSS VDDQ VREF K, /K SA0 to SA19 DQa1 to DQd9 /SS /SW /SBa /SBb /SBc /SBd /G ZZ ZQ M1, M2 NC TMS TDI TCK TDO Description Core Power Supply Ground Output Power Supply Input Reference Main Clock Synchronous Address Input Synchronous Data Input / Output Synchronous Chip Select Synchronous Byte Write Enable Synchronous Byte "a" Write Enable Synchronous Byte "b" Write Enable Synchronous Byte "c" Write Enable Synchronous Byte "d" Write Enable Asynchronous Output Enable Asynchronous Sleep Mode Output Impedance Control Mode Select No Connection Test Mode Select (JTAG) Test Data Input (JTAG) Test Clock Input (JTAG) Test Data Output (JTAG) Selects operation mode
Note
Function Supplies power for RAM core
Supplies power for output buffers
Logically selects SRAM Write command Write DQa1 to DQa9 Write DQb1 to DQb9 Write DQc1 to DQc9 Write DQd1 to DQd9 Asynchronous input Enables sleep mode, active high
Note This device only supports Single Differential Clock, R/R Mode. (R/R stands for Registered Input / Registered Output.)
Data Sheet M16379EJ4V0DS
3
PD44323362
Late Write Block Diagram
SA0 to SA19 K /K /SS K /K /SS
Address register Write address register Write clock genelator
Mux
/SW
/SW
/SBa
/SBa Write control logic
Memory array Read comp.
/SBb
/SBb
Data Data in out
/SBc
/SBc
/SBd
/SBd
Mux
DQ
Data in register
Output Register
/G
/G
ZZ
ZZ
4
Data Sheet M16379EJ4V0DS
PD44323362
Programmable Impedance / Power Up Requirements An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 ohm and 350 ohm. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. The impedance update of the output driver occurs only when the SRAM is in high impedance. Write and Deselect operations will synchronously switch the SRAM into and out of high impedance, therefore, triggering an update. Power up requirements for the SRAM are that VDD must be powered before or simultaneously with VDDQ followed by VREF; inputs should be powered last. The limitation on VDDQ is that it must not exceed VDD during power up. In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4096 clock cycles of power-up time after VDD reaches its operating range. And CID impedance is not updated during the clock stopped. Sleep Mode Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep Mode, the output will go to a high impedance state and the SRAM will draw standby current. SRAM data will be preserved and a recovery time (tZZR) is required before the SRAM resumes normal operation. And CID impedance is not updated during the sleep mode.
Data Sheet M16379EJ4V0DS
5
PD44323362
Synchronous Truth Table
ZZ L L L L L H /SS H L L L L x /SW /SBa /SBb /SBc /SBd x H L L L x x x L L H x x x L H L x x x L H L x x x L H L x Mode Not selected Read Write Write Write Sleep Mode DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 High-Z Dout Din Din High-Z High-Z High-Z Dout Din High-Z Din High-Z High-Z Dout Din High-Z Din High-Z High-Z Dout Din High-Z Din High-Z Power Active Active Active Active Active Standby
Remark x : Don't care
Output Enable Truth Table
Mode Read Read Sleep (ZZ = H) Write (/SW = L) Deselect (/SS = H) /G L H x x x DQ Dout High-Z High-Z High-Z High-Z
Mode Select (I/O)
M1 VSS
Note 1
M2 VDD
Mode Single Differential Clock (K, /K), R/R Mode
Note 2
Notes
1. This device only supports Single Differential Clock, R/R Mode. Mode Select Pins (M1, M2) are to be tied to either VDD or VSS. 2. R/R: Registered Input / Registered Output
Mode Select (Output Buffer)
ZQ IZQ x RQ VDD Mode Controlled impedance push-pull output buffer mode Push-pull output buffer mode Note 1 2
Notes
1. See figure.
ZQ
2. See figure.
VDD ZQ
6
Data Sheet M16379EJ4V0DS
PD44323362
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Output supply voltage Input voltage Input / Output voltage Junction temperature Storage temperature Symbol VDD VDDQ VIN VI/O Tj Tstg Condition MIN. -0.5 -0.5 -0.5 -0.5 5 -55 TYP. MAX. +3.0 +3.0 VDD + 0.3 (3.0 V MAX) VDD + 0.3 (3.0 V MAX) 110 +125 Unit V V V V C C Note 1 1 1 1
Note 1. -1.0 V MIN. (Pulse width 10% Tcyc) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (Tj = 5 to 110 C)
Parameter Core supply voltage Output buffer supply voltage Input reference voltage Low level input voltage High level input voltage Symbol VDD VDDQ VREF VIL VIH Conditions MIN. 2.375 1.4 0.68 -0.3
Note
TYP. 2.5
MAX. 2.625 1.9 0.95 VREF - 0.1 VDDQ + 0.3
Unit V V V V V
VREF + 0.1
Note -1.0 V MIN. (Pulse width 10% Tcyc) Recommended AC Operating Conditions (Tj = 5 to 110 C)
Parameter Input reference voltage Low level input voltage High level input voltage Symbol VREF (RMS) VIL VIH Conditions MIN. -5% -0.3 VREF + 0.2 TYP. MAX. +5% VREF - 0.2 VDDQ + 0.3 Unit V V V
Capacitance (TA Note = 25 C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Clock input capacitance
Note
Symbol CIN CI/O Cclk VIN = 0 V VI/O = 0 V Vclk = 0 V
Test conditions
MAX. 6 7 7
Unit pF pF pF
Note TA = Operating ambient temperature Remark These parameters are sampled and not 100% tested.
Data Sheet M16379EJ4V0DS
7
PD44323362
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Input leakage current DQ leakage current Operating supply current Symbol ILI ILO ICC VIN = 0 to VDD VI/O = 0 to VDDQ, /SS = VIH or /G = VIH VIN = VIH or VIL, /SS = VIL, ZZ = VIL, cycle = 250 MHz, IDQ = 0 mA Quiescent active power supply current Sleep mode power supply current Power supply standby current ISBSS ISBZZ ICC2 VIN = VIH or VIL, /SS = VIL, ZZ = VIL, Cycle = 4 MHz, IDQ = 0 mA ZZ = VIH, All other inputs = VIH or VIL, Cycle = DC, IDQ = 0 mA VIN = VIH or VIL, /SS = VIH, ZZ = VIL, Cycle = 250 MHz, IDQ = 0 mA 300 mA 150 mA 250 mA Conditions MIN. -5 -5 TYP. MAX. +5 +5 550 Unit
A A
mA
Output Voltage on Controlled Impedance Push-Pull Output Buffer Mode (VZQ = IZQ x RQ)
Parameter Low level output voltage Symbol VOL Conditions IOL = (VDDQ/2) / (RQ/5) 15% @VOL = VDDQ / 2 (175 < RQ < 350 ) High level output voltage VOH IOH = (VDDQ/2) / (RQ/5) 15% @VOH = VDDQ / 2 (175 < RQ < 350 ) VDDQ/2 VDDQ V MIN. VSS TYP. MAX. VDDQ/2 Unit V
Output Voltage on Push-Pull Output Buffer Mode (VZQ = VDD)
Parameter Low level output voltage High level output voltage Symbol VOL VOH IOL = +4 mA IOH = -4 mA Conditions MIN. - VDDQ - 0.3 TYP. MAX. 0.3 - Unit V V
8
Data Sheet M16379EJ4V0DS
PD44323362
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions (TA Note = 0 to 70 C, VDD = 2.375 to 2.625 V, VDDQ = 1.5 V)
Parameter High level input voltage Low level input voltage Input reference voltage Input rise time Input fall time Input and output timing reference level Symbol VIH VIL VREF TR TF Conditions 1.25 0.25 0.75 0.5 0.5 Cross point Unit V V V ns ns
Note TA = Operating ambient temperature Remark Parameter tested with RQ = 250 and VDDQ = 1.5 V. Input waveform (rise and fall time = 0.5 ns (20 to 80%))
1.25 V VTT or VDDQ / 2 0.25 V
Output waveform
VTT or VDDQ / 2
Data Sheet M16379EJ4V0DS
9
PD44323362
Read and Write Cycle
Parameter Clock cycle time Clock phase time Setup times Address Write data Write enable Chip select Hold times Address Write data Write enable Chip select Clock access time K high to Q change /G low to Q valid /G low to Q change /G high to Q High-Z K high to Q High-Z (/SW) K high to Q High-Z (/SS) K high to Q Low-Z /G high Pulse width /G high to K high K high to /G low Sleep mode recovery Sleep mode enable Symbol tKHKH tKHKL / tKLKH tAVKH tDVKH tWVKH tSVKH tKHAX tKHDX tKHWX tKHSX tKHQV tKHQX tGLQV tGLQX tGHQZ tKHQZ tKHQZ2 tKHQX2 tGHGL tGHKH tKHGL tZZR tZZE - 0.5 - 0.5 1.0 1.0 1.0 0.7 4.0 1.0 2.5 2 - 2.0 - 2.0 - 2.0 2.5 2.5 - - - - - 2 ns ns ns ns ns ns ns ns ns ns ns Cycle Cycle 3 3 3 4 4 1 2 1 2 2 2 2 0.5 - ns MIN. 4.0 1.5 0.5 MAX. - - - Unit ns ns ns Note
Notes 1. See figure. (VTT = 0.75 V, RQ = 250 )
VTT 50
Zo = 50 DQ (Output)
2. See figure. (VTT = 0.75 V, RQ = 250 )
VTT 50 DQ (Output) 5 pF
3. Controlled impedance push-pull output buffer mode only. 4. /SS must be 'high' before sleep mode entry.
10
Data Sheet M16379EJ4V0DS
Read Operation
/K K tAVKH Address a tSVKH /SS tKHWX tWVKH /SW tGHGL
Data Sheet M16379EJ4V0DS
tKHAX
tKHKH
tKHKL
tKLKH
b tKHSX
c
d
e
f
g
h
i
j
k
/G tGLQX tGHQZ High-Z tGLQV Qe Qf Qg tKHQZ2 High-Z tKHQX2
DQ
Qa tKHQX tKHQV
Qb
Qc
Qi
PD44323362
11
12
Write Operation
/K K tAVKH Address l tSVKH /SS tKHWX tWVKH /SW tGHKH tKHGL
Data Sheet M16379EJ4V0DS
tKHAX
tKHKH
tKHKL
tKLKH
m tKHSX
n
o
p
q
r
s
t
u
v
/G tGLQX tGHQZ High-Z tGLQV tKHQZ High-Z tKHQX2
DQ
Ql tDVKH
Dn
Qo
Qp
Qq
Ds
Qt
tKHDX
PD44323362
Sleep Mode
/K K
Address
a
b
c
d
e
f
g
h
i
j
k
l
/SS
Data Sheet M16379EJ4V0DS
/ZZ tZZE High-Z tZZR
DQ
Qa
Qb
Qc
Qj
PD44323362
13
PD44323362
JTAG Specifications
The PD44323362 supports a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins
Pin name TCK TMS TDI Pin assignments 4U 2U 3U from the falling edge of TCK. Test Mode Select. This is the command input for the TAP controller state machine. Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 5U Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Description Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate
Remark
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (Tj = 5 to 110 C)
Parameter JTAG input high voltage JTAG input low voltage JTAG output high voltage JTAG output low voltage Symbol VIH VIL VOH VOL IOH = -8 mA IOL = 8 mA Conditions MIN. 2.2 -0.3 2.4 - TYP. MAX. VDD + 0.3 (3.0 V MAX) +0.5 - 0.4 Unit V V V V Note
14
Data Sheet M16379EJ4V0DS
PD44323362
JTAG AC Test Conditions (Tj = 5 to 110 C)
Input waveform (rise / fall time = 1 ns (20 to 80%)) %
VDD VDD / 2 0V Test Points VDD / 2
Output waveform
VDD / 2
Test Points
VDD / 2
Output load (VTT = 1.5 V)
VTT 50
Z0 = 50 TDO
Data Sheet M16379EJ4V0DS
15
PD44323362
JTAG AC Characteristics (Tj = 5 to 110 C)
Parameter Clock cycle time (TCK) Clock phase time (TCK) Setup time (TMS / TDI) Hold time (TMS / TDI) TCK low to TDO valid (TDO) Symbol tTHTH tTHTL / tTLTH tMVTH / tDVTH tTHMX / tTHDX tTLQV Conditions MIN. 100 40 10 10 - TYP. MAX. - - - - 20 Unit ns ns ns ns ns Note
JTAG Timing Diagram
16
Data Sheet M16379EJ4V0DS
PD44323362
Scan Register Definition (1)
Register name Description The instruction register holds the instructions that are executed by the TAP controller when it is moved Instruction register into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test Bypass register data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the ID register controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the Boundary register boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit's position in the boundary register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number
Scan Register Definition (2)
Register name Instruction register Bypass register ID register Boundary register Bit size 3 1 32 70 Unit bit bit bit bit
ID Register Definition
ID [31:28] vendor revision no. XXXX ID [27:12] part no. 0000 0000 0011 1100 ID [11:1] vendor ID no. ID [0] fix bit 00000010000 1
Data Sheet M16379EJ4V0DS
17
PD44323362
SCAN Exit Order
Bit no. Signal name Bump ID Bit no. Signal name Bump ID
1
M2
5R
36 37
SA16 SA18 SA9 SA10 SA13 SA12 DQc9 DQc8 DQc7 DQc6 DQc5 DQc4 DQc3 DQc2 DQc1 /SBc ZQ /SS SA19
3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SA1 SA8 SA4 SA7 ZZ DQa9 DQa8 DQa7 DQa6 DQa5 DQa4 DQa3 DQa2 DQa1 /SBa /K K /G /SBb DQb1 DQb2 DQb3 DQb4 DQb5 DQb6 DQb7 DQb8 DQb9 SA2 SA3 SA6 SA5 SA17 SA15
4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
NC /SW /SBd DQd1 DQd2 DQd3 DQd4 DQd5 DQd6 DQd7 DQd8 DQd9 SA11 SA14 SA0
4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N
70
M1
3R
18
Data Sheet M16379EJ4V0DS
PD44323362
JTAG Instructions
Instructions Description EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented EXTEST in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the RAM output are forced to high impedance any time the instruction is loaded. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in IDCODE capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. The BYPASS instruction is loaded in the instruction register when the bypass register is placed between BYPASS TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable SAMPLE input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. compliant. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive SAMPLE-Z drive state (high impedance) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. Moving the controller to shift-DR state then places the This functionality is not Standard 1149.1 boundary scan register between the TDI and TDO pins.
JTAG Instruction Cording
IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z BYPASS SAMPLE BYPASS BYPASS BYPASS 1 Note 1
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
Data Sheet M16379EJ4V0DS
19
PD44323362
TAP Controller State Diagram
1
Test-Logic-Reset 0 1 1 Select-DR-Scan 0 1 Capture-DR 0 1 Capture-IR 0 Select-IR-Scan 0 1
0
Run-Test / Idle
Shift-DR 1 1 Exit1-DR 0
0
Shift-IR 1 1 Exit1-IR 0
0
Pause-DR 1 0 Exit2-DR 1
0
Pause-IR 1 0 Exit2-IR 1
0
Update-DR 1 0
Update-IR 1 0
Disabling The Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected.
20
Data Sheet M16379EJ4V0DS
PD44323362
Run-Test/Idle
Update-IR Exit1-IR
Shift-IR
Exit2-IR
Exit1-IR
Shift-IR
Capture-IR Select-IR-Scan Select-DR-Scan Run-Test/Idle
Test Logic Operation (Instruction Scan)
IDCODE
Pause-IR
New Instruction
Test-Logic-Reset
TDI
Controller state
Instruction Register state
TDO TMS
TCK
Output Inactive
Data Sheet M16379EJ4V0DS
21
PD44323362
Test-Logic-Reset
Select-IR-Scan Select-DR-Scan
Run-Test/Idle
Update-DR Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR Select-DR-Scan
Instruction
IDCODE
Run-Test/Idle
Test Logic (Data Scan)
TDI
Output Inactive Controller state
Data Sheet M16379EJ4V0DS
22
Instruction Register state
TDO TMS
TCK
PD44323362
Package Drawing
119-PIN PLASTIC BGA (14x22)
E E1 wSB 4-C1.05 ZD ZE B
A D1 D
7 6 5 4 3 2 1
INDEX MARK
U T RPNML K J HGF EDCB A wSA
A 25 y1 S A2 S y S e A1 S AB
(UNIT:mm) ITEM D E D1 E1 w e A A1 A2 b x y y1 ZD ZE DIMENSIONS 14.000.20 22.000.20 12.00 19.50 0.30 1.27 2.060.30 0.600.10 1.46 0.750.15 0.15 0.15 0.35 3.19 0.84 P119F1-127-FJ1
b
x
M
Data Sheet M16379EJ4V0DS
23
PD44323362
Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD44323362. Type of Surface Mount Device
PD44323362F1-FJ1: 119-pin plastic BGA
24
Data Sheet M16379EJ4V0DS
PD44323362
Revision History
Edition/ Date This edition 4th edition/ May 2004 Throughout Throughout Page Previous edition Throughout Throughout Modification Deletion Ordering Information Preliminary Data Sheet Data Sheet Type of revision Location Description (Previous edition This edition)
PD44323182F1-C40-FJ1 PD44323182F1-C50-FJ1 PD44323362F1-C50-FJ1
Data Sheet M16379EJ4V0DS
25
PD44323362
[MEMO]
26
Data Sheet M16379EJ4V0DS
PD44323362
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.
Data Sheet M16379EJ4V0DS
27
PD44323362
* The information in this document is current as of May, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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